MIT Spinout

MIT Spinout Vertical Semiconductor Raises $11M to Revolutionize AI Power Chips

Vertical Semiconductor, a new spinout from MIT, just landed $11 million in seed funding to push a disruptive approach in AI power circuitry. At its heart: a vertical architecture built on gallium nitride (GaN) that could trim energy waste and manage heat more elegantly than today’s power conversion chips.


From MIT labs to the power electronics frontier

Vertical began as a research project at MIT under Professor Tomás Palacios. His group explored how GaN devices might be reconfigured for denser, cooler, more efficient power conversion. The startup coalesced around work by doctoral researcher Joshua Perozek and others, with Cynthia Liao (MIT Sloan alum) taking the CEO mantle.

Key backers include Playground Global (lead), JIMCO Technology Ventures, milemark·capital, and Shin-Etsu Chemical. The new capital will underpin prototype development, manufacturing scale plans, and initial customer outreach.


What makes Vertical’s tech different

To grasp the novelty, let’s break down current limitations:

  • Power conversion losses: When huge voltages from utility lines are stepped down to microchip-friendly levels, a sizable fraction turns into waste heat.
  • Thermal management burden: That heat must be removed, adding complexity, cost, and energy overheads.
  • Footprint constraints: Traditional horizontal transistor layouts spread laterally, limiting density.

Vertical aims to disrupt all three by rethinking the transistor itself:

  • Vertical stacking of transistor elements: Instead of spreading transistors sideways, Vertical’s design stacks them upward. The result: more compact chips and shorter paths for current flow, which reduces resistance and heat.
  • GaN instead of silicon: GaN offers higher efficiency, faster switching, and better power density. Many in the industry already view GaN as a successor to silicon in specialized power electronics.
  • Compatibility with standard fabs: Vertical has demonstrated its technology on 8-inch wafers using conventional CMOS processes, which helps reduce the barrier to adoption.

The company claims that this vertical GaN architecture can shrink power module sizes by up to 50% and improve energy efficiency by up to 30% compared to legacy alternatives.


Why AI workloads make this a pivotal moment

AI models and data centers demand ever-larger power envelopes. But scaling compute without improving power delivery is like installing a jet engine and keeping a garden hose to feed it.

  • Infrastructure strain: Today’s AI training and inference farms consume enormous electricity; inefficiencies in voltage conversion become major drains.
  • Competitive edge: Every percent of efficiency saved is bottom-line value for cloud providers and AI operators.
  • Market dynamics: Existing players — Renesas, Infineon, Power Integrations — are exploring GaN designs, often in collaboration with Nvidia.
  • Cost & cooling pressure: If Vertical’s claims hold, it could reduce cooling infrastructure needs and electricity bills — a double win.

In short: Vertical is trying to shift power delivery from auxiliary support function to strategic lever.


Challenges and caveats ahead

Of course, the road is steep. Here are hurdles to watch:

  • Process yield & defects: New architectures often struggle with defect rates and scaling reproducibility.
  • Thermal and reliability validation: Long-term stability under load cycles is crucial for real-world use.
  • Customer adoption inertia: Large data center operators are conservative — getting them to adopt novel power tech is nontrivial.
  • Competing GaN strategies: Other firms are working on GaN power converters too; Vertical must deliver a clear differentiation.
  • Time to revenue: Prototyping is underway, but mass production and volume shipments will take time.

Vertical plans early sampling of prototype packaged devices by year-end, with fully integrated solutions targeting 2026.


What to watch next

Here are key milestones and indicators:

  1. Prototype performance — The first lab data will reveal how far Vertical’s claims can translate to reality.
  2. Partnerships and pilot deals — Deals with hyperscale cloud or AI providers will validate adoption.
  3. Production scaling — Ability to move from lab scale to wafer-level volumes, with acceptable yields.
  4. Thermal and reliability benchmarks — Sustained performance over years will build trust.
  5. Competitive responses — How legacy chip firms or Nvidia partners adapt, or counter.

Final take

Vertical Semiconductor’s $11 million raise signals more than just another AI startup funding headline. It reflects the growing recognition that power delivery — not just compute cores — is becoming a choke point for scaling AI.

If Vertical delivers on its promises, we could see a shift: power electronics redefined, infrastructure more efficient, and a new battleground in AI hardware. If not, the path is fraught with technical and market risks. Either way, Vertical’s journey is one to watch for anyone interested in the future of compute.

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